/*  Copyright (C) 2007 NXP B.V.
    All Rights Reserved.
*//**
    @file   include/asm-mips/mach-pnx833x/kernel-entry-init.h
    @brief  Pre-kernel initialisation

@b  Component:  Linux

*//*

Rev Date        Author      Comments
--------------------------------------------------------------------------------
  1 20061106   batelaan    Initial
  2 20061205   batelaan    Beautify
  3 20061205   batelaan    Crosscheck fixes
  4 20070611   steel       fix cache race condition
  5 20070910   batelaan    Moved to linux kernel-entry-init.h file
  5 20070924   batelaan    Correct load_dsp_info_addr.

--------------------------------------------------------------------------------
    For consistency and standardisation retain the Section Separators.
*/

#ifndef __ASM_MACH_PNX833X_KERNEL_ENTRY_H
#define __ASM_MACH_PNX833X_KERNEL_ENTRY_H

/*******************
* INCLUDE FILES    *
********************/

#include <asm/addrspace.h>
#include <asm/asm.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/cacheops.h>

/******************************************************************************/
/* Only perform this special processing for the second MIPS, the Audio MIPS. */
#ifdef CONFIG_PNX8335_AUDIO_MIPS

//#define PH_STBBOOTDSP_VERBOSE 1

/******************************************************************************/
.macro load_dsp_info_addr reg
	PTR_LA \reg, _text
	/* WARNING See file $PRJROOT/src/comps/phStbBootDsp/src/phStbBootDsp_Internal.h
	   The value that follows should match PH_STBBOOTDSP_DSP_INFO_SIZE */
	li k0, 0x20
	sub \reg, \reg, k0
.endm

/** Area where mips_cache_reset can operate. Uses tmp field of boot info structure. */
.macro 	LOAD_CACHE_INIT_ADDRESS reg
	load_dsp_info_addr t1
	lw \reg, 24(t1)
.endm

/*
 * cacheop macro to automate cache operations
 * first some helpers...
 */
#define _mincache(size, maxsize) \
   bltu  size,maxsize,9f ; \
   move  size,maxsize ;    \
9:

#define _align(minaddr, maxaddr, linesize) \
   .set noat ; \
   subu  AT,linesize,1 ;   \
   not   AT ;        \
   and   minaddr,AT ;      \
   addu  maxaddr,-1 ;      \
   and   maxaddr,AT ;      \
   .set at

/* general operations */
#define doop1(op1) \
   cache op1,0(a0)
#define doop2(op1, op2) \
   cache op1,0(a0) ;    \
   nop ;          \
   cache op2,0(a0)

/* specials for cache initialisation */
#define doop1lw(op1) \
   lw zero,0(a0)
#define doop1lw1(op1) \
   cache op1,0(a0) ;    \
   lw zero,0(a0) ;      \
   cache op1,0(a0)
#define doop121(op1,op2) \
   cache op1,0(a0) ;    \
   nop;           \
   cache op2,0(a0) ;    \
   nop;           \
   cache op1,0(a0)

#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
   .set  noreorder ;    \
10:   doop##tag##ops ;  \
   bne     minaddr,maxaddr,10b ; \
   add      minaddr,linesize ;   \
   .set  reorder

/* finally the cache operation macros */
#define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
   blez  n,11f ;        \
   addu  n,kva ;        \
   _align(kva, n, cacheLineSize) ; \
   _oploopn(kva, n, cacheLineSize, tag, ops) ; \
11:

#define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
   _mincache(n, cacheSize);   \
   blez  n,11f ;        \
   addu  n,kva ;        \
   _align(kva, n, cacheLineSize) ; \
   _oploopn(kva, n, cacheLineSize, tag, ops) ; \
11:

#define vcacheop(kva, n, cacheSize, cacheLineSize, op) \
   vcacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))

#define icacheop(kva, n, cacheSize, cacheLineSize, op) \
   icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))

/******************************************************************************/
/** Initialises UART1 to 8N1. */
.macro uart_init
#ifdef PH_STBBOOTDSP_VERBOSE
	/* Point t5 UART0 registers (0xb7e0b000) */
	/* Point t5 UART1 registers (0xb7e0c000) */
	lui t5, 0xb7e1
	addiu t5, t5, -0x4000

	/* UART line fifo control = 8N1 (b7e0b000 := 01000000) */
	lui v0, 0x100
	sw v0,0x0(t5)

	/* UART control/status = DCD+CTS etc. (b7e0b004 := 00900003) */
	lui v0,0x90
	addiu v0, v0, 0x3
	sw v0,0x4(t5)

	/* UART baud rate = 115200 (b7e0b008 := 00000001) */
	addiu v0,zero,0x1
	sw v0,0x8(t5)

	/* UART configuration = no flow control (b7e0b00c := 00000000) */
	sw zero,0xC(t5)
#endif
.endm

/******************************************************************************/
.macro uart_write char
#ifdef PH_STBBOOTDSP_VERBOSE
	/* Assumes t5 contains UART base.
	   Tramples over t6. */

	addiu t6,zero,\char
	sw t6, 0x28(t5)
\@:
	lw t6, 0x28(t5)
	srl t6, t6,0x10
	andi t6, t6, 0x1f
	bgtz t6, \@b
	nop
#endif
.endm

/******************************************************************************/
.macro mips_cache_reset

/* 16KB is the maximum size of instruction and data caches on
 * MIPS 4K.
 */
#define MIPS_MAX_CACHE_SIZE	0x4000
#define CFG_ICACHE_SIZE		16384
#define CFG_DCACHE_SIZE		8192
#define CFG_CACHELINE_SIZE	16
#define MIPS_MAX_CACHE_SIZE	0x4000


	li	t2, CFG_ICACHE_SIZE
	li	t3, CFG_DCACHE_SIZE
	li	t4, CFG_CACHELINE_SIZE


	li	v0, MIPS_MAX_CACHE_SIZE

	/* Now clear that much memory starting from specified address.
	 */

	LOAD_CACHE_INIT_ADDRESS a0
	uart_write 'b'
	addu	a1, a0, v0

2:	sw	zero, 0(a0)
	sw	zero, 4(a0)
	sw	zero, 8(a0)
	sw	zero, 12(a0)
	sw	zero, 16(a0)
	sw	zero, 20(a0)
	sw	zero, 24(a0)
	sw	zero, 28(a0)
	addu	a0, 32
	bltu	a0, a1, 2b

	uart_write 'c'
	/* Set invalid tag.
	 */

	mtc0	zero, CP0_TAGLO
	uart_write 'd'

   /*
    * The caches are probably in an indeterminate state,
    * so we force good parity into them by doing an
    * invalidate, load/fill, invalidate for each line.
    */

	/* Assume bottom of RAM will generate good parity for the cache.
	 */

	LOAD_CACHE_INIT_ADDRESS a0
	move	a2, t2		# icacheSize
	move	a3, t4		# icacheLineSize
	move	a1, a2
	icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill))
	uart_write 'e'
	/* To support Orion/R4600, we initialise the data cache in 3 passes.
	 */

	/* 1: initialise dcache tags.
	 */

	LOAD_CACHE_INIT_ADDRESS a0
	move	a2, t3		# dcacheSize
	li	a3, CFG_CACHELINE_SIZE
	move	a1, a2
	icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
	uart_write 'f'

	/* 2: fill dcache.
	 */

	LOAD_CACHE_INIT_ADDRESS a0
	move	a2, t3		# dcacheSize
	li	a3, CFG_CACHELINE_SIZE
	move	a1, a2
	icacheopn(a0,a1,a2,a3,1lw,(dummy))
	uart_write 'f'

	/* 3: clear dcache tags.
	 */

	LOAD_CACHE_INIT_ADDRESS a0
	move	a2, t3		# dcacheSize
	li	a3, CFG_CACHELINE_SIZE
	move	a1, a2
	icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
	uart_write 'g'

.endm


.set    noreorder
.align  5

/******************************************************************************/
/* macro, used in head.S.
 */
.macro kernel_entry_setup

	uart_init

loop:
    load_dsp_info_addr t1

	/* dummy read to flush CDMMU cache; at least 32 bytes removed from next read. */
	lw t3, 100(t1)

	/* prevent looping on crash during boot development */
	lw t2, 16(t1)
	bne t2,zero,loop
	nop

	/* Set booting field to non-zero in info structure so this function loops without UART printing
        when called again if an exception during boot up occurs */
	LONG_S	t1,16(t1)

	uart_write ' '
	uart_write 'B'

	/* Clear watch registers.
	 */
	mtc0	zero, CP0_WATCHLO
	mtc0	zero, CP0_WATCHHI

	/* STATUS register */
	mfc0	k0, CP0_STATUS
	li	k1, ~ST0_IE
	and	k0, k1
	mtc0	k0, CP0_STATUS

	/* CAUSE register */
	mtc0	zero, CP0_CAUSE

	/* Init Timer */
	mtc0	zero, CP0_COUNT
	mtc0	zero, CP0_COMPARE

	/* CONFIG0 register */
	li	t0, CONF_CM_UNCACHED
	mtc0	t0, CP0_CONFIG

	uart_write 'C'

	mips_cache_reset

	/* ... disable dcache
	 */
	mfc0	t0, CP0_CONFIG
	li	t2, -8
	and	t0, t0, t2
	ori	t0, t0, CONF_CM_UNCACHED
	mtc0    t0, CP0_CONFIG

	uart_write 'D'

	/* Load Linux kernel arguments 1-4 into a0-a3 registers: */
	lw a0, 0(t1)
	lw a1, 4(t1)
	lw a2, 8(t1)
	or a3, zero, zero


	/* Set stack pointer: */
	lw sp, 20(t1)
	uart_write 'J'
.endm

#else // #ifndef CONFIG_PNX8335_AUDIO_MIPS

.macro kernel_entry_setup
.endm

#endif // #ifndef CONFIG_PNX8335_AUDIO_MIPS

/******************************************************************************/
/*
 * Do SMP slave processor setup necessary before we can savely execute C code.
 */
.macro smp_slave_setup
.endm


#endif /* __ASM_MACH_PNX833X_KERNEL_ENTRY_H */
