#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/hardirq.h>
#include <linux/interrupt.h>
#include <asm/mipsregs.h>
#include <asm/irq_cpu.h>
#include <irq.h>
#include <gpio.h>
#if defined (CONFIG_TIME_DOCTOR)
#include <linux/timedoctor.h>
#endif

/*  Interrupt priority table. 
    0 = no interrupt generated, 15 = highest priority 
    Interrupts of priority 9 and above are not affected by calls to 
    tmosalDisableInterrupts(). See phStbOsal/src/linux/misc.c for details
*/

#define HIVID_PRI   11  /* critical video interrupts                         */
#define AUDIO_PRI   10  /* critical audio interrupts                         */
#define LOVID_PRI   9   /* less critical video interrupts                    */
#define OTHER_PRI   8   /* other high priority interrupts (maskable by osal) */

static const unsigned int irq_prio[PNX833X_PIC_NUM_IRQ] =
{
    0,          //unused
    4,          //PNX833X_PIC_I2C0_INT                 1
    4,          //PNX833X_PIC_I2C1_INT                 2
    1,          //PNX833X_PIC_UART0_INT                3
    1,          //PNX833X_PIC_UART1_INT                4
    6,          //PNX833X_PIC_TS_IN0_DV_INT            5
    6,          //PNX833X_PIC_TS_IN0_DMA_INT           6
    7,          //PNX833X_PIC_GPIO_INT                 7
    4,          //PNX833X_PIC_AUDIO_DEC_INT            8 (MIPS 1-2 Mailbox)
    5,          //PNX833X_PIC_VIDEO_DEC_INT            9
    4,          //PNX833X_PIC_CONFIG_INT              10
    AUDIO_PRI,  //PNX833X_PIC_AOI_INT                 11 (Audio IO. Very hard deadline. ~70Hz)
    LOVID_PRI,  //PNX833X_PIC_SYNC_INT                12 (SD Video sync. 50-60Hz)
    OTHER_PRI,  //PNX8335_PIC_SATA_INT                13
    4,          //PNX833X_PIC_OSD_INT                 14
    LOVID_PRI,  //PNX833X_PIC_DISP1_INT               15
    LOVID_PRI,  //PNX833X_PIC_DEINTERLACER_INT        16
    LOVID_PRI,  //PNX833X_PIC_DISPLAY2_INT            17
    4,          //PNX833X_PIC_VC_INT                  18
    4,          //PNX833X_PIC_SC_INT                  19
    OTHER_PRI,  //PNX833X_PIC_IDE_INT                 20
    OTHER_PRI,  //PNX833X_PIC_IDE_DMA_INT             21
    6,          //PNX833X_PIC_TS_IN1_DV_INT           22
    6,          //PNX833X_PIC_TS_IN1_DMA_INT          23
    4,          //PNX833X_PIC_SGDX_DMA_INT            24
    4,          //PNX833X_PIC_TS_OUT_INT              25
    4,          //PNX833X_PIC_IR_INT                  26
    3,          //PNX833X_PIC_VMSP1_INT               27
    3,          //PNX833X_PIC_VMSP2_INT               28
    4,          //PNX833X_PIC_PIBC_INT                29
    4,          //PNX833X_PIC_TS_IN0_TRD_INT          30
    4,          //PNX833X_PIC_SGDX_TPD_INT            31
    5,          //PNX833X_PIC_USB_INT                 32
    4,          //PNX833X_PIC_TS_IN1_TRD_INT          33
    4,          //PNX833X_PIC_CLOCK_INT               34
    4,          //PNX833X_PIC_SGDX_PARSER_INT         35
    4,          //PNX833X_PIC_VMSP_DMA_INT            36
#if defined(CONFIG_SOC_PNX8335)
    4,          //PNX8335_PIC_MIU_INT                 37
    4,          //PNX8335_PIC_AVCHIP_IRQ_INT          38
    HIVID_PRI,  //PNX8335_PIC_SYNC_HD_INT             39 (HD Video sync. Very hard deadline. 50-60Hz)
    LOVID_PRI,  //PNX8335_PIC_DISP_HD_INT             40
    LOVID_PRI,  //PNX8335_PIC_DISP_SCALER_INT         41
    4,          //PNX8335_PIC_OSD_HD1_INT             42
    4,          //PNX8335_PIC_DTL_WRITER_Y_INT        43
    4,          //PNX8335_PIC_DTL_WRITER_C_INT        44
    4,          //PNX8335_PIC_DTL_EMULATOR_Y_IR_INT   45
    4,          //PNX8335_PIC_DTL_EMULATOR_C_IR_INT   46
    4,          //PNX8335_PIC_DENC_TTX_INT            47
    4,          //PNX8335_PIC_MMI_SIF0_INT            48
    4,          //PNX8335_PIC_MMI_SIF1_INT            49
    4,          //PNX8335_PIC_MMI_CDMMU_INT           50
    4,          //PNX8335_PIC_PIBCS_INT               51
    2,          //PNX8335_PIC_ETHERNET_INT            52
    3,          //PNX8335_PIC_VMSP1_0_INT             53
    3,          //PNX8335_PIC_VMSP1_1_INT             54
    4,          //PNX8335_PIC_VMSP1_DMA_INT           55
    4,          //PNX8335_PIC_TDGR_DE_INT             56
    4,          //PNX8335_PIC_IR1_IRQ_INT             57
#endif
};

static void pic_dispatch(void)
{
	unsigned int irq = PNX833X_REGFIELD(PIC_INT_SRC, INT_SRC);

	if ((irq >= 1) && (irq < (PNX833X_PIC_NUM_IRQ)))
	{
		unsigned long priority = PNX833X_PIC_INT_PRIORITY;
		PNX833X_PIC_INT_PRIORITY = irq_prio[irq];

		if (irq == (PNX833X_PIC_GPIO_INT-PNX833X_PIC_IRQ_BASE))
		{
			unsigned long mask = PNX833X_PIO_INT_STATUS & PNX833X_PIO_INT_ENABLE;
			int pin;
			while ((pin = ffs(mask & 0xffff)))
			{
				pin -= 1;
#if defined (CONFIG_TIME_DOCTOR)
				timeDoctor_interrupt_enter(PNX833X_GPIO_IRQ_BASE + pin);
#endif
				do_IRQ(PNX833X_GPIO_IRQ_BASE + pin);
				gpio_clear_irq(pin);
#if defined (CONFIG_TIME_DOCTOR)
				timeDoctor_interrupt_exit(PNX833X_GPIO_IRQ_BASE + pin);
#endif
				mask &= ~(1 << pin);
			}
		}
		else
		{
#if defined (CONFIG_TIME_DOCTOR)
			timeDoctor_interrupt_enter(irq + PNX833X_PIC_IRQ_BASE);
#endif
			do_IRQ(irq + PNX833X_PIC_IRQ_BASE);
#if defined (CONFIG_TIME_DOCTOR)
			timeDoctor_interrupt_exit(irq + PNX833X_PIC_IRQ_BASE);
#endif

		}

		PNX833X_PIC_INT_PRIORITY = priority;
	}
	else
	{
		/* The PIC specification states that it is possible for the  */
		/* PIC interrupt to be asserted, but the intterupt source is */
		/* de-asseted 'for various reasons' and that the ISR should  */
		/* 'cope with the situation' ... consider it coped with!     */
	}
}

asmlinkage void plat_irq_dispatch(void)
{
	unsigned int pending = read_c0_status() & read_c0_cause();

	if (pending & STATUSF_IP4)
	{
		pic_dispatch();
	}
	else if (pending & STATUSF_IP7)
	{
		do_IRQ(PNX833X_TIMER_IRQ);
	}
	else
	{
		spurious_interrupt();
	}
}

static inline void pnx833x_hard_enable_pic_irq(unsigned int irq)
{
	/* Currently we do this by setting IRQ priority to 1.
	   If priority support is being implemented, 1 should be repalced
		by a better value. */
	PNX833X_PIC_INT_REG(irq) = irq_prio[irq];
}

static inline void pnx833x_hard_disable_pic_irq(unsigned int irq)
{
	/* Disable IRQ by writing setting it's priority to 0 */
	PNX833X_PIC_INT_REG(irq) = 0;
}

static int irqflags[PNX833X_PIC_NUM_IRQ];	/* initialized by zeroes */
#define IRQFLAG_STARTED		1
#define IRQFLAG_DISABLED	2

static DEFINE_SPINLOCK(irq_lock);

static unsigned int pnx833x_startup_pic_irq(unsigned int irq)
{
	unsigned long flags;
	unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;

	spin_lock_irqsave(&irq_lock, flags);
	
	irqflags[pic_irq] = IRQFLAG_STARTED;	/* started, not disabled */
	pnx833x_hard_enable_pic_irq(pic_irq);
	
	spin_unlock_irqrestore(&irq_lock, flags);
	return 0;
}

static void pnx833x_shutdown_pic_irq(unsigned int irq)
{
	unsigned long flags;
	unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;

	spin_lock_irqsave(&irq_lock, flags);
	
	irqflags[pic_irq] = 0;			/* not started */
	pnx833x_hard_disable_pic_irq(pic_irq);
	
	spin_unlock_irqrestore(&irq_lock, flags);
}

static void pnx833x_enable_pic_irq(unsigned int irq)
{
	unsigned long flags;
	unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;

	spin_lock_irqsave(&irq_lock, flags);
	
	irqflags[pic_irq] &= ~IRQFLAG_DISABLED;
	if (irqflags[pic_irq] == IRQFLAG_STARTED)
	{
		pnx833x_hard_enable_pic_irq(pic_irq);
	}
	spin_unlock_irqrestore(&irq_lock, flags);
}

static void pnx833x_disable_pic_irq(unsigned int irq)
{
	unsigned long flags;
	unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;

	spin_lock_irqsave(&irq_lock, flags);
	
	irqflags[pic_irq] |= IRQFLAG_DISABLED;
	pnx833x_hard_disable_pic_irq(pic_irq);
	
	spin_unlock_irqrestore(&irq_lock, flags);
}

static DEFINE_SPINLOCK(gpio_irq_lock);

static unsigned int pnx833x_startup_gpio_irq(unsigned int irq)
{
	int pin = irq - PNX833X_GPIO_IRQ_BASE;
	unsigned long flags;
	spin_lock_irqsave(&gpio_irq_lock, flags);
	gpio_enable_irq(pin);
	spin_unlock_irqrestore(&gpio_irq_lock, flags);
	return 0;
}

static void pnx833x_enable_gpio_irq(unsigned int irq)
{
	int pin = irq - PNX833X_GPIO_IRQ_BASE;
	unsigned long flags;
	spin_lock_irqsave(&gpio_irq_lock, flags);
	gpio_enable_irq(pin);
	spin_unlock_irqrestore(&gpio_irq_lock, flags);
}

static void pnx833x_disable_gpio_irq(unsigned int irq)
{
	int pin = irq - PNX833X_GPIO_IRQ_BASE;
	unsigned long flags;
	spin_lock_irqsave(&gpio_irq_lock, flags);
	gpio_disable_irq(pin);
	spin_unlock_irqrestore(&gpio_irq_lock, flags);
}

static int pnx833x_set_type_gpio_irq(unsigned int irq, unsigned int flow_type)
{
	int pin = irq - PNX833X_GPIO_IRQ_BASE;
	int gpio_mode;

	switch (flow_type)
	{
		case IRQ_TYPE_EDGE_RISING:
			gpio_mode = GPIO_INT_EDGE_RISING;
			break;
		case IRQ_TYPE_EDGE_FALLING:
			gpio_mode = GPIO_INT_EDGE_FALLING;
			break;
		case IRQ_TYPE_EDGE_BOTH:
			gpio_mode = GPIO_INT_EDGE_BOTH;
			break;
		case IRQ_TYPE_LEVEL_HIGH:
			gpio_mode = GPIO_INT_LEVEL_HIGH;
			break;
		case IRQ_TYPE_LEVEL_LOW:
			gpio_mode = GPIO_INT_LEVEL_LOW;
			break;
		default:
			gpio_mode = GPIO_INT_NONE;
			break;
	}

	gpio_setup_irq(gpio_mode, pin);

	return 0;
}

static struct irq_chip pnx833x_pic_irq_type = {
	.typename = "PNX-PIC",
	.startup = pnx833x_startup_pic_irq,
	.shutdown = pnx833x_shutdown_pic_irq,
	.enable = pnx833x_enable_pic_irq,
	.disable = pnx833x_disable_pic_irq,
};

static struct irq_chip pnx833x_gpio_irq_type = {
	.typename = "PNX-GPIO",
	.startup = pnx833x_startup_gpio_irq,
	.shutdown = pnx833x_disable_gpio_irq,
	.enable = pnx833x_enable_gpio_irq,
	.disable = pnx833x_disable_gpio_irq,
	.set_type = pnx833x_set_type_gpio_irq
};

void __init arch_init_irq(void)
{
	unsigned int irq;

	/* setup standard internal cpu irqs */
	mips_cpu_irq_init();

	/* Set IRQ information in irq_desc */
	for (irq = PNX833X_PIC_IRQ_BASE; irq < (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ); irq++)
	{
		pnx833x_hard_disable_pic_irq(irq);
		set_irq_chip_and_handler(irq, &pnx833x_pic_irq_type, handle_simple_irq);
	}

	for (irq = PNX833X_GPIO_IRQ_BASE; irq < (PNX833X_GPIO_IRQ_BASE + PNX833X_GPIO_NUM_IRQ); irq++)
	{
		set_irq_chip_and_handler(irq, &pnx833x_gpio_irq_type, handle_simple_irq);
	}

	/* Set PIC priority limiter register to 0 */
	PNX833X_PIC_INT_PRIORITY = 0;

	/* Setup GPIO IRQ dispatching */
	pnx833x_startup_pic_irq(PNX833X_PIC_GPIO_INT);
	
	/* Enable PIC IRQs (HWIRQ2) */
	if (cpu_has_vint)
	{
		set_vi_handler(4, pic_dispatch);
	}

	write_c0_status(read_c0_status() | IE_IRQ2);
}


void __init plat_time_init(void)
{
	/* calculate mips_hpt_frequency based on PNX833X_CLOCK_CPUCP_CTL reg */

	extern unsigned long mips_hpt_frequency;	
	unsigned long reg = PNX833X_CLOCK_CPUCP_CTL;
	
	if (!(PNX833X_BIT(reg, CLOCK_CPUCP_CTL, EXIT_RESET)))
	{
		/* Functional clock is disabled so use crystal frequency */
		mips_hpt_frequency = 25;

	}
	else
	{
#if defined(CONFIG_SOC_PNX8335)
		/* Functional clock is enabled, so get clock multiplier */
		mips_hpt_frequency = 90 + (10 * PNX8335_REGFIELD(CLOCK_PLL_CPU_CTL, FREQ));
#else
		static const unsigned long int freq[4] = {240, 160, 120, 80};
		mips_hpt_frequency = freq[PNX833X_FIELD(reg, CLOCK_CPUCP_CTL, DIV_CLOCK)];
#endif
	}

	printk("CPU clock is %ld MHz\n", mips_hpt_frequency);

	mips_hpt_frequency *= 500000;
}

