/*
 * Copyright 2010 Trident Microsystems (Far East) Ltd. All rights reserved.
 * All prior copyright rights in this work and the accompanying software
 * products transferred to Trident Microsystems (Far East) Ltd. by written
 * agreement.
 */
/*****************************************************************************/
/* Copyright (c) 2010 NXP B.V.  All rights are reserved.                     */
/*                                                                           */
/* Redistribution and use in source and binary forms, with or without        */
/* modification, are permitted provided that the following conditions        */
/* are met:                                                                  */
/*                                                                           */
/* Redistributions of source code must retain the above copyright            */
/* notice, this list of conditions and the following disclaimer.             */
/*                                                                           */
/* Redistributions in binary form must reproduce the above copyright         */
/* notice, this list of conditions and the following disclaimer in the       */
/* documentation and/or other materials provided with the distribution.      */
/*                                                                           */
/* Neither the name of NXP nor the names of its                              */
/* contributors may be used to endorse or promote products derived from      */
/* this software without specific prior written permission.                  */
/*                                                                           */
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS       */
/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT         */
/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR     */
/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT      */
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/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT          */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,     */
/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY     */
/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT       */
/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE         */
/* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH          */
/* DAMAGE.                                                                   */
/*                                                                           */
/*****************************************************************************/

/* Configuration C21 (mips=320 ddr=166 256MB) */

	li t0, 0x5b007ffa	/* clk_pll_ddr_m_ctl (DDR clock) */
	li t1, 0xB7e09018
	sw t0, 0x0(t1)
	li t0, 0x000400e2	/* clk_pll_ddr_np_ctl */
	li t1, 0xB7e0901c
	sw t0, 0x0(t1)
	li t0, 0x77EFBFFF	/* reset_control */
	li t1, 0xb7e08004
	sw t0, 0x0(t1)
	li t0, 0x0000007f	/* reset_control2 */
	li t1, 0xb7e08014
	sw t0, 0x0(t1)
	li t0, 0x00009C40	/* SIF0_DCNT (Setup SIF0) */
	li t1, 0xb7e03000
	sw t0, 0x0(t1)
	li t0, 0x00003553	/* SIF0_MEM_CONF */
	li t1, 0xb7e03004
	sw t0, 0x0(t1)
	li t0, 0x000003c0	/* SIF0_REFRESH_PERIOD */
	li t1, 0xb7e03008
	sw t0, 0x0(t1)
	li t0, 0x00000008	/* SIF0_TRAS_TIMING */
	li t1, 0xb7e0300c
	sw t0, 0x0(t1)
	li t0, 0x00000003	/* SIF0_TRCD_TIMING */
	li t1, 0xb7e03010
	sw t0, 0x0(t1)
	li t0, 0x00000003	/* SIF0_TWR_TIMING */
	li t1, 0xb7e03014
	sw t0, 0x0(t1)
	li t0, 0x00000003	/* SIF0_TRP_TIMING */
	li t1, 0xb7e03018
	sw t0, 0x0(t1)
	li t0, 0x0000000E	/* SIF0_TRFC_TIMING */
	li t1, 0xb7e0301c
	sw t0, 0x0(t1)
	li t0, 0x00000002	/* SIF0_TRRD_TIMING */
	li t1, 0xb7e03020
	sw t0, 0x0(t1)
	li t0, 0x00000002	/* SIF0_TWTR_TIMING */
	li t1, 0xb7e03024
	sw t0, 0x0(t1)
	li t0, 0x00000002	/* SIF0_TRTW_TIMING */
	li t1, 0xb7e03028
	sw t0, 0x0(t1)
	li t0, 0x00000002	/* SIF0_TMRD_TIMING */
	li t1, 0xb7e03030
	sw t0, 0x0(t1)
	li t0, 0x00000002	/* SIF0_SAMP_LATENCY */
	li t1, 0xb7e03040
	sw t0, 0x0(t1)
	li t0, 0x00000003	/* SIF0_RESET */
	li t1, 0xb7e03ff4
	sw t0, 0x0(t1)
	li t0, 0x00009C40	/* SIF1_DCNT (Setup SIF1) */
	li t1, 0xb7e54000
	sw t0, 0x0(t1)
	li t0, 0x00003553	/* SIF1_MEM_CONF */
	li t1, 0xb7e54004
	sw t0, 0x0(t1)
	li t0, 0x000003c0	/* SIF1_REFRESH_PERIOD */
	li t1, 0xb7e54008
	sw t0, 0x0(t1)
	li t0, 0x00000008	/* SIF1_TRAS_TIMING */
	li t1, 0xb7e5400c
	sw t0, 0x0(t1)
	li t0, 0x00000003	/* SIF1_TRCD_TIMING */
	li t1, 0xb7e54010
	sw t0, 0x0(t1)
	li t0, 0x00000003	/* SIF1_TWR_TIMING */
	li t1, 0xb7e54014
	sw t0, 0x0(t1)
	li t0, 0x00000003	/* SIF1_TRP_TIMING */
	li t1, 0xb7e54018
	sw t0, 0x0(t1)
	li t0, 0x0000000E	/* SIF1_TRFC_TIMING */
	li t1, 0xb7e5401c
	sw t0, 0x0(t1)
	li t0, 0x00000002	/* SIF1_TRRD_TIMING */
	li t1, 0xb7e54020
	sw t0, 0x0(t1)
	li t0, 0x00000002	/* SIF1_TWTR_TIMING */
	li t1, 0xb7e54024
	sw t0, 0x0(t1)
	li t0, 0x00000002	/* SIF1_TRTW_TIMING */
	li t1, 0xb7e54028
	sw t0, 0x0(t1)
	li t0, 0x00000002	/* SIF1_TMRD_TIMING */
	li t1, 0xb7e54030
	sw t0, 0x0(t1)
	li t0, 0x00000002	/* SIF1_SAMP_LATENCY */
	li t1, 0xb7e54040
	sw t0, 0x0(t1)
	li t0, 0x00000003	/* SIF1_RESET */
	li t1, 0xb7e54ff4
	sw t0, 0x0(t1)
	li t0, 0x00000007	/* CLK_PCP_CTL (PI clock) */
	li t1, 0xb7e09204
	sw t0, 0x0(t1)
	li t0, 0x157	/* CLK_PLL_CPU_CTL (MIPS clock) */
	li t1, 0xb7e09020
	sw t0, 0x0(t1)
	li t0, 0x77FFBFFF	/* reset_control */
	li t1, 0xb7e08004
	sw t0, 0x0(t1)
	li t0, 0x01bf000f	/* cdmmu_config (single vs dual sif) */
	li t1, 0xb7e05084
	sw t0, 0x0(t1)
